What Type Of Register Is The Alu

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[SOLVED] ALU Design on VIVADO for RISCV Compages

• Thread starter michaelScott
• Kickoff date May 18, 2022

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How-do-you-do people,
I am designing a RISCV ALU on VIVADO and i desire all the instructions as sub-blocks equally seen the lawmaking beneath(conduct-lookahead adder/subtractor). I want merely i carry-lookahead adder/subtractor in the ALU for the dissimilar instructions like add and decrease. Tin y'all help me about that. In the output i run across only high impedance.

                                  `timescale 1ns / 1ps module alu(     input [31:0] Ten, //pedagogy input     input [31:0] A, //information input     input [31:0] B, //data input     output reg [31:0] C     );      wire [31:0] add together, sum; wire C5; carry_lookahead M0(A, B, 0, add, C5); carry_lookahead M1(A, B, one, sum, C5);  ///////////////////////// R TYPE ///////////////////////// wire [6:0] funct7; //reg [4:0] rs2;  //address //reg [4:0] rs1;  //address wire [ii:0] funct3; //reg [4:0] rd;  //accost wire [half-dozen:0] opcode; ///////////////////////// I TYPE ///////////////////////// wire [11:0] imm; //reg [iv:0] rs1; //register adress //wire [2:0] funct3; //reg [4:0] rd;  //register adress //wire [6:0] opcode; ///////////////////////////////////////////////////////////  wire [31:0] imm_i; assign imm_i = {{20{imm[11]}}, imm[eleven:0]}; wire [31:0] sum_imm; carry_lookahead M2(A, imm_i, 0, sum_imm, C5);  assign funct7 = X[31:25]; //assign rs2 = Ten[24:xx]; //assign rs1 = X[19:fifteen]; assign funct3 = X[14:12]; //assign rd = X[11:seven]; assign opcode = X[6:0];  assign imm = 10[31:20];  always @(funct7[5], funct3, opcode, A, B) begin C = 0; case (opcode)     7'b0110011: case(funct3)         3'b000: case(funct7[5])             1'b0: C = add together;  //add together             1'b1: C = sum;  //sum             endcase         3'b001: C = A << B;  //sll         3'b010: C = (A < B) ? i'b1 : one'b0;  //slt(signed)         3'b011: C = (A < B) ? one'b1 : 1'b0;  //sltu(unsigned)         3'b100: C = A ^ B;    //xor         3'b110: C = A | B;    //or         3'b111: C = A & B;    //and         endcase     7'b0010011: case(funct3)         3'b000: C = sum_imm;    //addi         three'b010: C = (A < imm_i) ? 1'b1 : 1'b0;  //slti(signed)         3'b011: C = (A < imm_i) ? i'b1 : 1'b0;  //sltiu(signed)         3'b100: C = A ^ imm_i;//xori         3'b110: C = A | imm_i;//ori         three'b111: C = A & imm_i;//andi         endcase                                                  endcase end endmodule                                

--- Updated May 18, 2022 ---

I improved the blueprint every bit seen beneath simply i go mistake about the out signal.
What do i do wrong.
thanks in advance

                                  `timescale 1ns / 1ps module alu(     input [31:0] X, //didactics input     input [31:0] A, //data input     input [31:0] B, //data input     output reg [31:0] C     );      reg [31:0] in1, in2, out; reg M, C5; carry_lookahead M0(in1, in2, Yard, out, C5);  ///////////////////////// R Type ///////////////////////// wire [vi:0] funct7; //reg [4:0] rs2;  //address //reg [4:0] rs1;  //accost wire [2:0] funct3; //reg [four:0] rd;  //accost wire [vi:0] opcode; ///////////////////////// I TYPE ///////////////////////// wire [xi:0] imm; //reg [4:0] rs1; //register adress //wire [2:0] funct3; //reg [4:0] rd;  //register adress //wire [6:0] opcode; ///////////////////////////////////////////////////////////  wire [31:0] imm_i; assign imm_i = {{20{imm[11]}}, imm[xi:0]};  assign funct7 = X[31:25]; //assign rs2 = X[24:20]; //assign rs1 = X[19:15]; assign funct3 = X[14:12]; //assign rd = X[11:7]; assign opcode = X[6:0];  assign imm = X[31:20];  always @(funct7[5], funct3, opcode) begin C = 0; case (opcode)     7'b0110011: case(funct3)         3'b000: instance(funct7[5])             1'b0: begin                     in1 = A;                     in2 = B;                     G = 0;                     out = C;  //add                     finish             i'b1: begin                     in1 = A;                     in2 = B;                     M = 1;                     out = C;  //sum                     end             endcase         3'b001: C = A << B;  //sll         3'b010: C = (A < B) ? one'b1 : ane'b0;  //slt(signed)         3'b011: C = (A < B) ? 1'b1 : 1'b0;  //sltu(unsigned)         3'b100: C = A ^ B;    //xor         3'b110: C = A | B;    //or         3'b111: C = A & B;    //and         endcase     7'b0010011: instance(funct3)         3'b000: begin                 in1 = A;                 in2 = imm_i;                 Thousand = 0;                 out = C;  //addi                 end            3'b010: C = (A < imm_i) ? one'b1 : 1'b0;  //slti(signed)         3'b011: C = (A < imm_i) ? one'b1 : 1'b0;  //sltiu(signed)         three'b100: C = A ^ imm_i;//xori         three'b110: C = A | imm_i;//ori         3'b111: C = A & imm_i;//andi         endcase                                                  endcase finish endmodule                                

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Last edited: May xviii, 2022

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What Type Of Register Is The Alu,

Source: https://www.edaboard.com/threads/alu-design-on-vivado-for-riscv-architecture.402583/

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